Programmable Logic Devices (PLD), such as field programmable gate arrays (FPGA) and other semiconductor devices have a bonded set of channels. These bonded channels have intentional skew compensation, either active or passive, to ensure that rising and falling edges of data coincide as nearly as possible in time with each other. For example, the Assignee's STRATIX™ II GX PLD utilizes a quad architecture, where four full duplex (transmit and receive) channels may be grouped to a common clock. A buffer amplifier on the clock line facilitates clocking an adjacent quad, accumulating the buffer delay in the skew. In this architecture, up to eight channels, i.e., two quads, can be bonded thereby resulting in all eight lines being within one clock buffer delay of each other as far as signal edge placement is concerned.
Recent developments have arisen where skew-aligned bonded signals of widths greater than eight bits are required. For example, Fully Buffered Dual In-line Memory Modules (FBDIMM) require ten bonded transmit channels, which may be referred to as lanes, which operate at speeds up to 4.8 Gbps per lane. In addition, Digital-to-Analog Converters (DAC) are currently available that require interfaces of 13 or 14 transmit bits that are operating at approximately 1.4 to 1.8 GSamples/sec for numerous radio frequency (RF) Direct Digital Synthesis (DDS) applications. Even within the test and measurement arena, as many vectors as possible need to be delivered simultaneously to a device under test. Given the current architecture described above, the lack of support for an application that requires more than eight bonded channels is becoming an issue.
Accordingly, there is a need to adapt the current architecture which provides groups of eight bonded channels to support devices requiring a greater number than eight bonded channels.